Fujitsu MB91460 manuali

Fujitsu MB91460 Manuale Utente (1038 pagine)

Marchio: Fujitsu | Categoria: Convertitori video | Dimensione: 10.50 MB |

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Indice

MB91460 Series

1

User’s Manual

1

- PRELIMINARY

1

FUJITSU LIMITED

2

Chapter 1 Introduction

17

Chapter 1 Introduction

18

1.How to Handle the Device

18

2. Instruction for Users

19

■ Caution: PS register

20

■ Watchdog timer function

20

2.Instruction for Users

21

■ Operand break

22

4. How to Use This Document

23

Reserved

25

4.How to Use This Document

26

2.1 FR60 CPU Core

27

2.2 Instruction Cache

27

2.Features

28

2.10 Peripheral Function

30

4. Block Diagram

37

4.Block Diagram

38

1. Memory Map

39

2. I/O Map

40

Register

42

+0 +1 +2 +3

42

3. Interrupt Vector Table

89

4. Package

94

5. Pin Assignment Diagram

95

6. Pin Definitions

96

6.Pin Deﬁnitions

100

7. I/O Circuit Type

110

8. Pin State Table

112

8.Pin State Table

113

Chapter 4 CPU Architecture

121

2. Features

122

Chapter 4 CPU Architecture

123

6. Instruction Overview

124

7. Data Structure

125

8. Word Alignment

126

9. Addressing

127

9.Addressing

128

Chapter 5 CPU Registers

129

2.1 PC: Program Counter

130

[Initial value]

131

D1 D0 T XX0

131

20 19 18 17 16

132

ILM3 ILM2 ILM1 ILM0

132

■ Caution: PS Register

133

2.3 TBR: Table-base Register

134

2.4 RP: Return Pointer

134

2.6 USP: User Stack Pointer

135

■ At the executing division

136

1. Overview

137

3. EIT Trigger

137

4. Return from EIT

137

5. EIT Interrupt Level

138

6. EIT Vector Table

138

7. Multiple EIT Processing

139

7.Multiple EIT Processing

140

8. Operation

141

8.1 User Interrupt operation

141

■ Operation

142

8.6 Coprocessor Absent Trap

144

8.7 Coprocessor Error Trap

144

9. Caution

144

Chapter 7 Branch Instruction

145

3.2 RET:D Instruction

146

3.3 Bcc:D rel Instruction

146

3.4 CALL:D Instruction

146

4.2 Step Trace Trap

147

4.3 Interrupt

147

3. State Transition Diagram

150

3.1 RUN (Normal Operation)

151

3.2 SLEEP

151

3.3 STOP

151

3.State Transition Diagram

153

Chapter 9 Reset

155

4.3 MOD: Mode Pins

160

4.4 Mode Vector

160

4.5 Reset Vector

160

4.6 Device Mode Overview

161

Chapter 9 Reset

162

8. Reset Operation Modes

166

9. MCU Operation Mode

167

10. Caution

168

10.Caution

169

Chapter 10 Standby

171

5. Operation

175

5.1 Sleep Mode

175

5.2 Stop mode

176

6. Settings

177

7. Q&A

177

7.Q&A

179

Chapter 10 Standby

179

Chapter 11 Memory Controller

183

7. Registers

184

8. Explanations of Registers

185

Chapter 11 Memory Controller

186

8.Explanations of Registers

186

Chapter 12 Instruction Cache

195

Chapter 12 Instruction Cache

196

2.Main body structure

196

● Control register structure

197

Figure 2-4 I-Cacheable Area

200

3. Operating mode conditions

201

● Cache Entry Update

202

Chapter 13 Clock Control

205

Chapter 13 Clock Control

206

INIT pin input

209

watchdog reset

209

4.Registers

213

5.Operation

215

5.3 Notes

216

7. Q & A

218

• CPU clock setting

219

• Peripheral clock setting

219

Chapter 14 PLL Interface

223

4.1 PLL Control Registers

224

5. Recommended Settings

228

Chapter 14 PLL Interface

230

6.Clock Auto Gear Up/Down

230

7. Caution

231

7.Caution

232

3. Registers

234

• Bit5-0: CAN clock disable

235

3.Registers

236

Chapter 16 Clock Supervisor

237

2. Clock Supervisor Register

238

Chapter 16 Clock Supervisor

239

2.Clock Supervisor Register

239

Clock Supervisor

240

4. Operation Modes

241

4.Operation Modes

242

Main Sub

249

Main Main

250

Main Sub Main

251

Main Stop Main

252

Chapter 17 Clock Modulator

255

2. Clock Modulator Registers

256

Chapter 17 Clock Modulator

257

2.Clock Modulator Registers

257

CMPRL (lower)

260

CMPRH (upper)

260

3. Application Note

263

● Recommended settings

264

Chapter 18 Timebase Counter

265

5.1 INIT Pin Input

269

(STCR.OSCD[2:1]=“11”):

271

Main Clock Mode

272

■ Timebase counter

273

■ “L” level input to INIT pin

273

■ Timebase timer

273

See figure below

274

Chapter 19 Timebase Timer

279

6. Setting

284

Chapter 19 Timebase Timer

288

■ Watchdog timer

289

2. Configuration

300

3. Register

301

4. Functions

303

5. Caution

304

1.Overview

305

4. Register

307

5.2 Interval Interrupt

309

Figure 5-1 Reference

319

Interval time

321

Chapter 24 Interrupt Control

327

(*1) : Used by REALOS

331

4.2 Interrupt Vector

333

7.4 How can I set an I ﬂag?

336

Chapter 25 External Interrupt

337

External interrupts 8 - 15

339

Figure 3-4 Register List

340

Clear by software

343

7.4 Interrupt types

345

Chapter 26 DMA Controller

349

■ Block Diagram

350

■ Notes on Setting Registers

351

Chapter 26 DMA Controller

352

(DMASA0 to 4/DMADA0 to 4)

366

(DMACR)

367

2.5 Other Functions

368

DMA pin function

369

● Edge detection

372

● Level detection

372

■ Built-in Peripheral Request

372

■ Software Request

372

3.2 Transfer Sequence

373

● Burst fly-by transfer

374

■ Block Size

376

■ Reload Operation

376

3.4 Addressing Mode

377

3.5 Data Types

378

3.6 Transfer Count Control

378

3.7 CPU Control

379

● Disabling all channels

382

■ Stopping Due To an Error

382

3.10 DMAC Interrupt Control

383

■ Channel Group

385

● For 2-cycle transfer

385

■ AC Characteristics of DMAC

388

4. Operation Flowcharts

389

■ Demand Transfer

390

4.Operation Flowcharts

391

5. Data Bus

392

5.Data Bus

393

6. DMA External Interface

395

■ Timing of Demand Transfer

396

■ Transfer Mode Settings

396

● 2-cycle transfer mode

396

6.DMA External Interface

398

Chapter 27 Delayed Interrupt

399

4.1 DICR:

400

Chapter 27 Delayed Interrupt

402

Chapter 28 Bit Search

403

Detection Data Register

405

• Execution example

407

7.1 How is data written?

410

7.2 How is scanning started?

410

7.3 How is a result read?

410

Chapter 28 Bit Search

412

Chapter 29 MPU / EDSU

413

3. Break Functions

415

3.2 Operand address break

416

Chapter 29 MPU / EDSU

417

3.Break Functions

417

3.3 Data value break

418

3.5 Memory Protection

420

3.6 Break Factors

421

4.1 List of EDSU Registers

423

SR SW SX UR UW UX FCPU FDMA

426

5. Quick Reference

445

5.Quick Reference

446

Chapter 30 I/O Ports

447

2. I/O Circuit Types

469

2.1 I/O Cell List MB91V460

469

3. Port Register Settings

470

3.1 General Rules

470

Chapter 30 I/O Ports

471

3.Port Register Settings

471

3.2 I/O Port Block Diagram

472

3.3 Port Input Enable

473

0 1 (default)

518

Chapter 31 External Bus

523

Chapter 31 External Bus

524

1.2 Block Diagram

525

1.3 I/O Pins

526

1.4 Register List

526

■ Register Types

528

(AWR0-7)

536

● Ordinary bus interface

559

● Time division I/O interface

559

4.1 Big Endian Bus Access

560

■ Data Bus Width

561

● 32-bit bus width

561

● 16-bit bus width

562

● 8-bit bus width

562

■ External Bus Access

562

● Word access

565

● Halfword access

566

● Byte access

566

■ Data Format

566

4.Endian and Bus Access

570

■ Word Access

571

■ Halfword Access

572

■ Byte Access

574

32-bit bus

575

16-bit bus

576

8-bit bus

577

5.1 Basic Timing

578

WRn + byte control type

579

■ Write -> Write Operation

581

5.5 Auto-Wait Cycle

582

5.6 External Wait Cycle

583

5.8 CSn Delay Setting

586

CSn delay setting

586

■ Burst Access Operation

590

6.Burst Access Operation

591

■ Without External Wait

592

■ With External Wait

593

■ CSn -> RD/WRn Setup

593

8. Prefetch Operation

595

8.Prefetch Operation

596

9.1 Self Refresh

600

9.2 Power-on Sequence

601

■ Address Multiplexing Format

602

Memory Connection Example

603

This LSI

605

SDRAM(No.1)

605

SDRAM(No.2)

605

SDRAM(No.3)

605

SDRAM(No.4)

605

10. DMA Access Operation

608

10.DMA Access Operation

609

● At SDRAM page misses

615

IOWR set to 00H

621

11. Bus Arbitration

624

11.Bus Arbitration

625

■ Notes for Use

627

Chapter 32 USART (LIN / FIFO)

629

■ USART operation modes

630

■ USART Interrupts

631

2. USART Configuration

632

2.USART Conﬁguration

633

3. USART Pins

636

4. USART Registers

637

4.USART Registers

638

■ Reception:

644

■ Transmission:

644

5. USART Interrupts

654

■ Transmission Interrupt

655

■ Bus Idle Interrupt

655

5.USART Interrupts

656

6. USART Baud Rates

658

6.1 Setting the Baud Rate

659

■ Counting Example

660

■ Programmable Restart

661

■ Automatic Restart

662

7. USART Operation

663

■ Transfer data format

664

■ Transmission Operation

664

■ Reception Operation

665

■ Signal mode NRZ and RZ

665

■ Clock Supply

666

■ Data signal mode

667

■ Error Detection

667

■ Communication

667

■ USART as LIN master

668

■ USART as LIN slave

668

■ LIN bus timing

669

■ USART Direct Pin Access

670

■ Inter-CPU Connection

671

■ Function Selection

672

■ Communication Procedure

673

7.USART Operation

674

■ LIN device connection

675

■ USART as master device

676

■ USART as slave device

677

8. Notes on using USART

679

Chapter 33 I

681

C Controller

681

Chapter 33 I2C Controller

682

C Interface Registers

683

■ Data Register (IDAR0)

684

2.I2C Interface Registers

686

IBSR0 register is ‘1’

694

2.7 Data Register (IDAR0)

697

■ Prescaler settings:

699

Data sending

700

C Interface Operation

701

■ Slave Address Masking

702

■ Addressing Slaves

702

■ Arbitration

702

■ Acknowledgement

702

4. Programming Flow Charts

703

Transfer End

703

■ Example Of Receiving Data

704

4.Programming Flow Charts

705

Chapter 34 CAN Controller

707

2. Register Description

708

2.1 Programmer’s Model

708

Chapter 34 CAN Controller

711

2.Register Description

711

■ Status Register (STATR)

714

■ Status Interrupts

716

■ Error Counter (ERRCNT)

716

■ Bit Timing Register (BTR)

717

■ Test Register (TESTR)

718

■ IFx Mask Registers (IFxMSK)

724

■ Interrupt Register (INTR)

730

■ New Data Registers (NEWDT)

732

3. Functional Description

736

3.1 Software Initialisation

736

3.2 CAN Message Transfer

736

3.4 Test Mode

737

3.5 Silent Mode

737

3.6 Loop Back Mode

737

3.8 Basic Mode

738

3.Functional Description

739

4. CAN Application

740

4.4 Transmission of Messages

741

4.6 Reception of Data Frame

742

4.CAN Application

744

4.16 Handling of Interrupts

745

4.17 Bit Time and Bit Rate

746

Figure 4-5 Bit Timing

747

Chapter 35 Free-Run Timer

749

3. Configuration Diagram

750

• bit4: Stop counting

752

7.6 Interrupt Types

759

Chapter 35 Free-Run Timer

762

Chapter 36 Input Capture

763

• When specifying rising edge

769

• Both edges

769

Chapter 37 Output Compare

775

Chapter 37 Output Compare

779

CST0 Operation

779

4.2 OCCP: Compare Register

780

(OCS67.OTD[1:0])

785

Chapter 38 Reload Timer

791

Figure 3-3 Register List

793

No.311)”

793

• bit1: Enable timer count

796

4.2 TMR: Timer Register

797

4.3 TMRLR: Reload register

797

Chapter 38 Reload Timer

799

5.5 Operation during Reset

801

5.9 Status Transition

802

PPG (0-3)

813

4.6 PTMR: PPG Timer Register

823

5.1 PWM Operation

824

5.2 One-Shot Operation

825

5.3 Restart Operation

826

1. PFM Overview

839

1.PFM Overview

840

2. Reload Counter Registers

842

2.Reload Counter Registers

843

● P0TMR, P1TMR structure

844

● P0TMRLR, P1TMRLR structure

845

3. Reload Counter Operation

846

Underflow operation

846

● Underflow operation timing

847

■ Counter Operation States

847

● Counter state transitions

848

4. PFM Operation and Setting

849

4.PFM Operation and Setting

850

Chapter 41 Up/Down Counter

851

Chapter 41 Up/Down Counter

853

Selector

854

Figure 3-5 Register List

855

Figure 3-6 Register List

855

• bit1,0: Up/down flag

860

■ 16 Bit Mode (M16E= “1”)

861

■ 8 Bit Mode (M16E=“0”)

861

■ 16 Bit Mode (M16E=“1”)

862

(1) Stop counting

863

5.1 Timer Mode CMS[1:0]=“00”

864

Reload value

865

Countdown

865

Interrupt

865

ZIN=Gate control

866

Count value

867

CSTR or ZIN gate function

869

Up/Down Counter

870

Chapter 42 Sound Generator

879

2. Block Diagram

880

3.1 Register Details

882

Chapter 42 Sound Generator

883

■ Tone Count Register (SGTR)

884

2. Registers

888

2.2 PWM Control Register

890

[bit 1 to 0] Reserved bits

891

H (200H)

893

H (3FFH)

893

000h3FFh 3FFh 000h 3FFh 000h

895

2.Registers

896

3. Operation

897

3.Operation

898

4. Caution

899

4.Caution

900

Chapter 44 A/D Converter

901

Chapter 44 A/D Converter

902

■ Register list

903

■ A/D enable register (ADER)

905

■ Single Mode

912

■ Continuous Mode

912

■ Stop Mode

912

4.Operation of A/D Converter

913

4.2 Scan conversion mode

914

5. Setting

915

6. Q & A

917

FST - VOT

923

(N+1)T - VNT

923

• Overall error

924

Chapter 45 D/A Converter

925

D/A converter (0-1)

926

4.1 DADR: D/A Data Register

927

Chapter 45 D/A Converter

928

MD08 Operation

928

0 D/A resolution is 10 bits

928

1 D/A resolution is 8 bits

928

8. Caution

932

Chapter 46 Alarm Comparator

933

Chapter 46 Alarm Comparator

934

4.1 Interrupt Mode (IEN=1)

935

4.2 Polling Mode (IEN=0)

935

Chapter 47 LCD Controller

937

Figure 3-2 Register List

939

• bit1-0: Frame period

941

Chapter 47 LCD Controller

943

7.2 How do I set VRM?

953

Chapter 48 Clock Monitor

957

• Other bits7-5, bits3-0

960

Chapter 48 Clock Monitor

964

Chapter 49 Real-Time Clock

965

Chapter 49 Real-Time Clock

973

1.1 Description

979

3. Timing

981

4. Clocks

982

5. Register Description

983

- - STRT - - INT INTEN

984

5.Register Description

985

6. Application Note

989

■ Accuracy:

990

■ Power dissipation:

990

■ Measurement limits:

990

Chapter 52 Regulator Control

995

Chapter 52 Regulator Control

998

2. Check for Boot Conditions

999

2.1 Evaluation Chip MB91V460

999

2.Check for Boot Conditions

1000

3.1 Evaluation Chip MB91V460

1004

4.Flash Access Mode Switching

1005

5.Bootloader Update Strategy

1006

Chapter 54 Flash Memory

1009

3. Configuration

1010

Chapter 54 Flash Memory

1011

3.Conﬁguration

1011

4. Registers

1012

5. Access Modes

1012

5.1 Access from the FR-CPU

1012

6.Flash Access Mode Switching

1013

6.1 Flash Memory Mode

1014

7. Auto Algorithms

1015

7.1 Command Operation

1015

7.2 Auto Algorithm Commands

1016

7.Auto Algorithms

1017

7.3 Hardware Sequence Flag

1019

8. Caution

1023

8.Caution

1024

Chapter 55 Flash Security

1025

3. Flash Security Vectors

1026

3.1 Vector addresses

1026

3.2 Security Vector FSV1

1026

■ FSV1 (bits 15 to 0)

1027

3.3 Security Vector FSV2

1028

4. Register

1029

Chapter 55 Flash Security

1032

4.Register

1032

Author : MBo

1035

Electronic Devices

1037

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