Fujitsu MB15F74UV Manuale Utente

Navigare online o scaricare Manuale Utente per no Fujitsu MB15F74UV. Fujitsu MB15F74UV User's Manual Manuale Utente

  • Scaricare
  • Aggiungi ai miei manuali
  • Stampa
  • Pagina
    / 25
  • Indice
  • SEGNALIBRI
  • Valutato. / 5. Basato su recensioni clienti
Vedere la pagina 0
DS04-21381-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual S
erial Input
PLL Frequency
Synthesizer
MB15F74UV
DESCRIPTION
The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting
the new circuit.
MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50% com-
paring with the former BCC20 (for dual PLL) .
FEATURES
High frequency operation : RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max
Low power supply voltage : VCC = 2.7 V to 3.6 V
Ultra low power supply current : I
CC = 9.0 mA Typ
(VCC = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)
(Continued)
PACKAGE
18-pin plastic BCC
(LCC-18P-M05)
Vedere la pagina 0
1 2 3 4 5 6 ... 24 25

Sommario

Pagina 1 - MB15F74UV

DS04-21381-1EFUJITSU SEMICONDUCTORDATA SHEETASSPDual Serial InputPLL Frequency SynthesizerMB15F74UV DESCRIPTIONThe Fujitsu MB15F74UV is a serial in

Pagina 2

MB15F74UV10• Prescaler Data Setting• Charge Pump Current Setting•LD/fout output Selectable Bit Setting• Phase Comparator Phase Switching Data Setting

Pagina 3

MB15F74UV113. Power Saving Mode (Intermittent Mode Control Circuit) The intermittent mode control circuit reduces the PLL power consumption.By settin

Pagina 4

MB15F74UV124. Serial Data Data Input TimingDivide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.Setting data

Pagina 5

MB15F74UV13 PHASE COMPARATOR OUTPUT WAVEFORM• LD Output LogicNotes : • Phase error detection range = −2π to +2π • Pulses on DoIF/RF signals during

Pagina 6

MB15F74UV14 TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) LD/foutDoIFVCCIF1000 pF0.1 µF0.1 µFPSIFGNDIFfinIFXfinIFGNDOSCINDoRFVCCRFPSRFG

Pagina 7

MB15F74UV15 TYPICAL CHARACTERISTICS1.fin input sensitivity101500 2000 2500 3000 3500 4000 4500 5000VCC = 2.7 VVCC = 3.0 VVCC = 3.6 VSPEC0−10−20−30−

Pagina 8

MB15F74UV162.OSCIN input sensitivity100 20 40 80 100 140 160VCC = 2.7 VVCC = 3.0 VVCC = 3.6 VSPEC0−10−20−30−40−5060 120Catalog guaranteed rangeInput s

Pagina 9

MB15F74UV173. RF/IF-PLL Do output current • 1.5 mA mode• 6.0 mA mode2.500.50−2.501.0 3.00.0 2.00.5 2.51.52.00−1.001.50−1.501.00−2.000.00−0.50VCC = 2.

Pagina 10

MB15F74UV184.fin input impedance494.28 Ω−874.84 Ω200 MHz58.094 Ω−216.47 Ω1 GHz39.773 Ω−148 Ω1.5 GHz1 : 2 : 3 : START 100.000 000 MHz STOP 2 000.000 00

Pagina 11

MB15F74UV195. OSCIN input impedanceOSCIN input impedance2.25 kΩ−2.2373 kΩ10 MHz881.62 Ω−1.8299 kΩ20 MHz448.75 Ω−1.353 kΩ30 MHz1 : 2 : 3 : START 3.000

Pagina 12

MB15F74UV2(Continued)• Direct power saving function : Power supply current in power saving mode Typ 0.1 µA (VCC = 3.0 V, Ta = +25 °C at 1 system) Max

Pagina 13

MB15F74UV20 REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) (Continued)Test CircuitS.G.OSCINfinDoLPFVCOSpectrumAnalyze

Pagina 14

MB15F74UV21(Continued)2.173604000 GHz2.173600000 GHz2.173596000 GHz4.500 ms2.000 msA Mkr x: 439.99764 µsy: 50.0009 MHz-500 µs500 µs/div2.113604000 GH

Pagina 15

MB15F74UV22 APPLICATION EXAMPLELD/foutDoIFVCCIF1000 pF0.1 µF0.1 µFPSIFGNDIFfinIFXfinIFGNDOSCINDoRFVCCRFPSRFGNDRFXfinRFfinRFLEDataClock1000 pF1000 p

Pagina 16

MB15F74UV23 USAGE PRECAUTIONS (1) VCCRF and VCCIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VC

Pagina 17

MB15F74UV24 PACKAGE DIMENSION18-pin plastic BCC (LCC-18P-M05) Dimensions in mm (inches) Note : The values in parentheses are reference values.C2003

Pagina 18

MB15F74UVFUJITSU LIMITEDAll Rights Reserved.The contents of this document are subject to change without notice. Customers are advised to consult with

Pagina 19

MB15F74UV3 PIN DESCRIPTIONPin no.Pin nameI/O Descriptions1GND Ground pin for OSC input buffer and the shift register circuit.2finIF IPrescaler inp

Pagina 20

MB15F74UV4 BLOCK DIAGRAM(10)ClockDataLEPSRFXfinRFfinRFOSCINfinIFPSIFVCCIF GNDIFfpIFDoIFLDIFT1 T2T1 T2FCRFSWRFLDSDoRFORLD/foutLDfrIFfrRFfpIFfpRFfrIF

Pagina 21

MB15F74UV5 ABSOLUTE MAXIMUM RATINGSWARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperatur

Pagina 22

MB15F74UV6 * ELECTRICAL CHARACTERISTICS (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)(Continued)Parameter Symbol ConditionValueUnitMin Typ MaxPowe

Pagina 23

MB15F74UV7(Continued) (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “0” in locking state.*2 : VCCI

Pagina 24

MB15F74UV8 FUNCTIONAL DESCRIPTION1. Pulse swallow functionfVCO = [ (P × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled

Pagina 25 - FUJITSU LIMITED

MB15F74UV9 (2) Data setting•Binary 14-bit Programmable Reference Counter Data Setting Note : Divide ratio less than 3 is prohibited.•Binary 11-bit Pro

Commenti su questo manuale

Nessun commento