Fujitsu MB86617A Manuale Utente

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI i IEEE1394 Serial Bus Controller for DTV MB86617A LSI Specification

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 5<< Asynchronous Transmit FIFO Extended Mode

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 958.13. Physical register #14, 15, 16 (read) Physical Register#14, 15, 16 are the registers tha

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 968.14. Physical register #17, 18, 19, 1A, 1B, 1C, 1D, 1E (read/write) Physical Register#17, 18

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 978.15. Link register #00 (read/write) Link Register#00 is the register that sets this node to

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 988.16. Link register #01 (read/write) Link Register#00 is the register that sets this node to

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 998.17. Link register #02 (read/write) Link Register#02 is the register that sets transfer mode

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 1008.18. Link register #03 (read/write) Link Register#03 is the register that performs Link lay

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 101Chapter 9 Instruction This chapter explains the instruction codes and details for respecti

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 1029.1. Instruction Code Table Instruction name code Operand Start sleep 01 Remove sleep

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 1039.2. Description of Each Instruction << Start sleep (01 h) This instruction changes t

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 104<< Asynchronous Send (31 h) This instruction transmits the data stored at the ASYNC

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 6<< Asynchronous Receive FIFO Extended Mode

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 105<< DMA Transmit (Asynchronous) (71h) This instruction writes in the transmit Asynch

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 106Chapter 10 Interrupt This chapter explains the inturrput-factors and method for interrupt-ma

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 10710.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register AD R/ Bit

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 10810.2. Interrupt Interrupt Interrupt Item INT1 Loop detected INT2 Self-ID packet error INT

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 10910.3. Description of Interrupt Each interrupt items are described below. Interrupt Inter

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 110 Interrupt Interrupt Item Description INT7 Isochronous cycle too long Isochronous cycle ex

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 111 Interrupt Interrupt Item Description INT23 Cycle start packet received Received cycle sta

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 112Chapter 11 Operation This chapter explains the operation of this device and displays the exa

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 11311.1. Initialization The example of control flow from the system power on to the packet tran

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 11411.2. Self-ID Packet Receiving The example of control flow for receiving Self-ID packet is s

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 73.2. Function of Each Block This section explains the function of each block for MB86617A. &l

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 115 11.2.1 Self-ID Packet Receive at Bus Reset Process This section explains the receiving pr

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 116 << Flow chart before bus reset completion <Host>

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 117<< Flow chart after bus reset completion <Host>

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 11811.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping Regardless of s-ID store

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 119<< Flow chart after receiving Self-ID packet <Host>

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 12011.3. Asynchronous Packet Transmitting The example of control flow for transmitting of Async

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 121<< Flow chart after storing transmitting data into Asynchronous transmit FIFO <Hos

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 12211.4. Asynchronous Packet Receiving The example of control flow for receiving Asynchronous p

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 123<< Flow chart for received data before storing in Asynchronous receive FIFO <Host&

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 124<< Flow chart for received data after storing in Asynchronous receive FIFO <Host&g

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 8Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 12511.5. Isochronous Packet Transmitting The example of control flow for transmitting Isochrono

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 126 <Host> <Device>

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 127 (Note)Register and bit necessary for transmitting are as follows. Data Address MPEG-TS DSS

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 12811.6. Isochronous Packet Receiving The example of control flow for receiving Isochronous pac

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 129 (Note)Register and bit necessary for receiving are as follows. Data Address MPEG-TS DSS D

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 130Chapter 12 System Configuration This chapter explains the system configuration of this chip.

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 13112.1. Recommended Connection for 1934 Port (for one port) The example of recommended connect

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 13212.2 Recommended Connection for Cable Power Supply The example of recommended connection of

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 13312.3. Recommended Connection for Build-in PLL Loop Filter The example of recommended connect

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 13412.4. Configuration of Feedback Circuit at Crystal Oscillator The example of configuration o

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 94.1. Pin Assignment The following diagram shows the MB86617A pin assignment. 8885807570

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 104.2. Corresponding Table of MB86617A Pin The following table shows the corresponding items of

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 114.3. Outline Drawing of Package This section shows the outline drawing of MB86617A package (L

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 12Chapter 5 Pin Function This chapter explains the MB86617A pin function. 5.1. IEEE1394 Inte

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 135.1. IEEE1394 Interface This section explains the pin function of IEEE1394 interface. Sign

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 145.2. Isochronous Interface This section explains the pin function of Isochronous interface.

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI ii Contents CHAPTER 1 OVERVIEW ...

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 15 IERRA O Output pin for noticing error of receive data (on port A) ‘H’ active signal IERRB

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 165.4. MPU Interface This section explains the pin function of MPU interface. Signal Name I/O

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 175.5. Other Pins This section explains the pin function like internal PLL. Signal Name I/

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 185.6. Power/GND Pin This section explains the power/GND pin. Signal Name I/O Function VDD

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 19Chapter 6 Internal Register This chapter explains the MB86617A internal register. Note that

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 20 WRITE READ Address (HEX) Register Name Register Name 20 transmit DSS packet header settin

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 21 WRITE READ Address (HEX) Register Name Register Name 50 (reserved) data bridge transmit

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 22 WRITE READ Address (HEX) Register Name Register Name 80 (reserved) transmit CGMS/TSCH i

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 23 WRITE READ Address (HEX) Register Name Register Name B0 (reserved) (reserved) B2 (res

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 24 WRITE READ Address (HEX) Register Name Register Name E0 (reserved) (reserved) E2 (res

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI iii 7.3. INSTRUCTION FETCH REGISTER...

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 25Chapter 7 Internal Register Function Description This chapter explains the details of the int

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 26 7.25. Receive Isochronous Packet Header Indicate Register 3 [B] 7.26. Receive Isochronous

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 277.1. M ode-control Register Mode-control register is the register that performs the relative

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 28 BIT Bit Name Action value Function 0 Uses 2K byte FIFO on LINK I/F side of bridge for I

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 297.2. flag & status Register flag & status register indicates the status of this LSI

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 30 BIT Bit Name Action Value Function 0 Indicates that the device is not in forced sleep. 4

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 317.3. instruction-fetch Register instruction-fetch register is the register that writes in in

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 327.4. interrupt-factor Indicate Register/interrupt-mask Setting Register interrupt-factor indi

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 337.5. Receive Acknowledge Indicate Register Receive Acknowledge indicate register is the regis

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 347.6. A-buffer Data Port Receive/Transmit This integrated register is the buffer access port f

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI iv 7.32. PING TIME MONITOR REGISTER...

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 357.7. TSP Transmit Information Setting Register [A] TSP transmit information setting register

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 36 BIT Bit Name Action Value Function 0 Selects CGMS information input from TSP -IC as EMI i

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 377.8. TSP Transmit Information Setting Register [B] TSP transmit information setting register

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 38 BIT Bit Name Action Value Function 0 Selects CGMS information input from TSP -IC as EMI i

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 397.9. Transmit Offset Setting Register [A] Transmit offset setting register [A] is the registe

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 407.10. Transmit Offset Setting Register [B] Transmit off set setting register [B] is the regis

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 417.11. TSP Receive Information Setting Register TSP receive information setting register perfo

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 42 BIT Bit Name Action Value Function 0 Deletes received data and reports FMT error when MP

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 43 Register setting value and selection of output port are shown in the table below. Bit 15 Bi

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 447.12. Receive DSS Packet Header Indicate Register [A]/Transmit DSS Packet Header Settin

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI v 9.2. DESCRIPTION OF EACH INSTRUCTION...

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 457.13. Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header Setting

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 467.14. TSP Status Register TSP status register indicates status of TSP -IC I/F. AD R/W Bit

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 47 BIT Bit Name Active Value Function 9~8 reserved Read - Always indicate ‘0’. 0 Indica

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 487.15. Data Bridge Transmit Information Setting Register 1 [A] Data bridge transmit informatio

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 497.16. Data Bridge Transmit Information Setting Register 2 [A] Data bridge transmit informatio

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 507.17. Data Bridge Transmit Information Setting Register 3 [B] Data bridge transmit informatio

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 517.18. Data Bridge Transmit Information Setting Register 4 [B] Data bridge transmit informatio

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 527.19. Data Bridge Receive Information Setting Register Data bridge receive information regist

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 537.20. Transmit Packet Link/Split Setting Register Transmit packet link/split setting register

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 54 BIT Bit Name Action Value Function 0 Executes 2SP combined transmission as FIFO NFULL ope

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 1Chapter 1 Overview This chapter explains the overview of MB86617A. MB86617A is Fujitsu’s IEEE

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 557.21. Late Packet Decision Range Setting Register [A] Late packet decision range setting reg

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 567.22. Late Packet Decision Range Setting Register [B] Late packet decision range setting reg

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 577.23. Receive Isochronous Packet Header Indicate Register 1 [A] Receive Isochronous packet he

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 587.24. Receive Isochronous Packet Header Indicate Register 2 [A] Receive Isochronous packet he

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 597.25. Receive Isochronous Packet Header Indicate Register 3 [B] Receive Isochronous packet he

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 607.26. Receive Isochronous Packet Header Indicate Register 4 [B] Receive Isochronous packet he

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 617.27. FIFO Reset Setting Register FIFO reset setting register sets force reset of bridge and

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 627.28. Data Bridge Transmit/Receive Status Register [A] Data bridge transmit/receive status re

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 63 BIT Bit Name Action Value Function 0 Indicates that the data length of received packet is

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 64 BIT Bit Name Action Value Function 0 Indicates that CIP header of received Isochronous p

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 2Chapter 2 Features This chapter explains the features of MB86617A. > Compliant with IEEE

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 657.29. Data Bridge Transmit/Receive Status Register [B] Data bridge transmit/receive status re

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 66 BIT Bit Name Action Value Function 0 Indicates that data length of receive packet is same

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 67 BIT Bit Name Action Value Function 0 Indicates that CIP header of received Isochronous p

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 687.30. Isochronous Channel Monitor Register Isochronous channel monitor register is the regist

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 697.31. Cycle-timer-monitor Indicate Register Cycle-timer-monitor indicate register indicates v

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 707.32. Ping Time Monitor Register Ping time monitor register is the register that indicates ti

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 717.33. PHY/LINK Register/Address Setting Register PHY/LINK register/address setting register i

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 727.34. PHY/LINK Register Access Port PHY/LINK register access port is the port to access PHY/L

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 737.35. Revision Indicate Register Revision indicate register is the register that indicates ch

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 747.36. Transmit CGMS/TSCH Indicate Register [A] Transmit CGMS/TSCH indicate register [A] indic

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 3Chapter 3 Chip Block This chapter explains the MB86617A block diagram and the function of each

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 757.37. Transmit CGMS/TSCH Indicate Register [B] Transmit CGMS/TSCH indicate register [B] indic

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 767.38. Transmit CGMS/TSCH Indicate Status Register Transmit CGMS/TSCH indicate status register

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 77 BIT Bit Name Action Value Function 0 Indicates that the packet indicated in CGMSA-1 and T

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 787.39. Transmit EMI/OE Setting Register Transmit EMI/OE setting register sets EMI information

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 79 BIT Bit Name Action Value Function 6 - 5 IPH EMI-A Read/ Write - Set EMI information whi

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 80Chapter 8 PHY/INK Register Function Description This chapter explains the Physical Register a

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 818.1. PHY/LINK Register Table Table of Physical Register and Link Register is shown below.

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 82 PHY/LINK addr Write Read 2Ch Physical register #17 ← 2Eh Physical register #18 ← 30h P

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 838.2. Physical register #00 (read) Physical Register#00 is the register that indicates Physica

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 848.3. Physical register #01 (read/write) Physical Register#01 is the register that set s/indic

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 43.1. Block Diagram MB86617A block diagram is shown below. << Normal Operation Mode

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 858.4. Physical register #02 (read) Physical Register#02 is the register that indicates if the

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 868.5. Physical register #03 (read) Physical Register#03 is the register that indicates max. tr

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 878.6. Physical register #04 (read/write) Physical Register#04 is the register that sets the pa

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 888.7. Physical register #05 (read/write) Physical Register#05 is the register indicating avail

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 89 BIT Bit Name Action Value Function 0 Indicates that port event and resume processing hav

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 908.8. Physical register #07, 08, 09 (read) Physical Register#07, 08, 09 are the registers that

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 918.9. Physical register #0A, 0B, 0C (read/write) Physical Register#0A, 0B, 0C are the register

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 928.10. Physical register #0D, 0E, 0F (read/write) Physical Register#0D, 0E, 0F are the regist

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 938.11. Physical register #10 (read) Physical Register#10 is the register that indicates Compli

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI 948.12. Physical register #11, 12, 13 (read) Physical Register#11, 12, 13 are the registers tha